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Features
* Permanent Software Write Protection for the First-half of the Array
- Software Procedure to Verify Write Protect Status
* Hardware Write Protection for the Entire Array * Low-voltage Operation
- 1.8 (VCC = 1.8V to 5.5V) Internally Organized 256 x 8 Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 100 kHz (1.8V) and 400 kHz (2.7V and 5.0V) Compatibility 16-byte Page Write Modes Partial Page Writes Are Allowed Self-timed Write Cycle (5 ms max) High-reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years * Automotive Grade Devices Available * 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP, and 8-ball dBGA2 Packages * Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
* * * * * * * * *
Two-wire Serial EEPROM with Permanent Software Write Protect
2K (256 x 8)
Description
The AT34C02 provides 2048 bits of serial electrically-erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a software write protection feature while hardware write protection for the entire array is available via an external pin as well. Once the software write protection is enabled, by sending a special command to the device, it cannot be reversed. The hardware write protection is controlled with the WP pin and can be used to protect the entire array, whether or not the software write protection has been enabled. This allows the user to protect none, first-half, or all of the array depending on the application. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT34C02 is available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead MAP, 8-lead TSSOP and 8-ball dBGA2 packages and is accessed via a two-wire serial interface. In addition, it is available in 1.8V (1.8V to 5.5V) versions. Table 1. Pin Configurations
Pin Name A0 - A2 SDA SCL WP Function Address Inputs Serial Data Serial Clock Input Write Protect 8-lead TSSOP
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA
A0 A1 A2 GND
AT34C02
Note: Not recommended for new design; please refer to AT34CO2C datasheet.
8-lead PDIP
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA
8-lead MAP
VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND
Bottom View 8-lead SOIC
1 2 3 4 8 7 6 5 VCC WP SCL SDA
8-ball dBGA2
VCC WP SCL SDA
8 7 6 5 1 2 3 4
A0 A1 A2 GND
Bottom View
Rev. 0958Q-SEEPR-1/07
1
Absolute Maximum Ratings*
Operating Temperature..................................-55C to +125 C Storage Temperature .....................................-65C to +150C Voltage on Any Pin with Respect to Ground .................................... -1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Figure 1. Block Diagram
VCC GND WP SCL SDA START STOP LOGIC SERIAL CONTROL LOGIC WRITE PROTECT CIRCUITRY LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 COMP LOAD INC X DEC DATA RECOVERY
SOFTWARE WRITE PROTECTED AREA (00H - 7FH)
EN
H.V. PUMP/TIMING
R/W
DATA WORD ADDR/COUNTER
EEPROM
Y DEC
SERIAL MUX
DIN
DOUT/ACK LOGIC DOUT
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Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under "Device Addressing," page 9.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10k or less. Table 2. AT34C02 Write Protection Modes
WP Pin Status VCC GND or Floating GND or Floating Write Protect Register - Not Programmed Programmed Part of the Array Write Protected Full Array (2K) Normal Read/Write First-Half of Array (1K: 00H - 7FH)
Table 3. Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V
Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V
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Table 4. DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, TAE = -40C to +125C, VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol VCC1 VCC2 ICC ICC ISB1 ISB2 ISB3 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 1.8V Standby Current VCC = 2.7V Standby Current VCC = 5.0V Input Leakage Current Output Leakage Current Input Low Level
(1)
Test Condition
Min 1.8 2.7
Typ
Max 5.5 5.5
Units V V mA mA A A A A A V V V V
READ at 100 kHz WRITE at 100 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS -0.6 VCC x 0.7 IOL = 2.1 mA IOL = 0.15 mA
0.4 2.0 0.6 1.6 8.0 0.10 0.05
1.0 3.0 3.0 4.0 18.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2
Input High Level(1) Output Low Level VCC = 3.0V Output Low Level VCC = 1.8V
1. VIL min and VIH max are reference only and are not tested.
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AT34C02
Table 5. AC Characteristics Applicable over recommended operating range from TAI = -40C to +85C, TAE = -40C to +125C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted).
1.8V Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Note: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time
(1)
2.7V, 5.0V Max 100 Min Max 400 1.2 0.6 100 50 0.1 1.2 0.6 0.6 0 100 1.0 300 0.3 300 0.6 50 5 5 1M 0.9 Units kHz s s ns s s s s s ns s ns s ns ms Write Cycles
Min
4.7 4.0
Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time Inputs Fall Time
(1)
0.1 4.7 4.0 4.7 0 200
4.5
(1)
Stop Set-up Time Data Out Hold Time Write Cycle Time 5.0V, 25C, Page Mode
4.7 100
1M
1. This parameter is characterized and is not 100% tested.
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Memory Organization Device Operation
AT34C02, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16 bytes each. Random word addressing requires a 8-bit data word address. CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5 on page 8). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 5 on page 8). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 5 on page 8). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT34C02 features a low-power standby mode which is enabled: (a) upon power-up or (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition.
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AT34C02
Figure 2. Bus Timing SCL: Serial Clock SDA: Serial Data I/O
Figure 3. Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O
SCL
SDA
8th BIT WORDn
ACK
twr STOP CONDITION
(1)
START CONDITION
Note:
1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
Figure 4. Data Validity
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Figure 5. Start and Stop Condition
Figure 6. Output Acknowledge
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AT34C02
Device Addressing
The 2K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 8 on page 12). The device address word consists of a mandatory one-zero sequence for the first four most-significant bits (1010) for normal read and write operations and 0110 for writing to the write protect register. The next 3 bits are the A2, A1 and A0 device address bits for the AT34C02 EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. The device will not acknowledge if the write protect register has been programmed and the control code is 0110.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, t WR , to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 9 on page 12). The device will acknowledge a write command, but not write the data, if the software or hardware write protection has been enabled. The write cycle time must be observed even when the write protection is enabled. PAGE WRITE: The 2K device is capable of 16-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 10 on page 13). The data word address lower four bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than sixteen data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. The device will acknowledge a write command, but not write the data, if the software or hardware write protection has been enabled. The write cycle time must be observed even when the write protection is enabled. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue.
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Write Protection
The software write protection, once enabled, permanently write protects only the firsthalf of the array (00H - 7FH) while the hardware write protection, via the WP pin, is used to protect the entire array. SOFTWARE WRITE PROTECTION: The software write protection is enabled by sending a command, similar to a normal write command, to the device which programs the write protect register. This must be done with the WP pin low. The write protect register is programmed by sending a write command with the device address of 0110 instead of 1010 with the address and data bit being don't cares (see Figure 7 on page 11). Once the software write protection has been enabled, the device will no longer acknowledge the 0110 control byte. The software write protection cannot be reversed even if the device is powered down. The write cycle time must be observed. HARDWARE WRITE PROTECTION: The WP pin can be connected to VCC, GND, or left floating. Connecting the WP pin to VCC will write protect the entire array, regardless of whether or not the software write protection has been enabled. The software write protection register cannot be programmed when the WP pin is connected to VCC. If the WP pin is connected to GND or left floating, the write protection mode is determined by the status of the software write protect register.
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AT34C02
WP Connected to GND or Floating Start 1010 1010 1010 0110 0110 0110 0110 R/W Bit R W W R R W W Write Protect Register X Programmed Not Programmed Programmed Not Programmed Programmed Not Programmed Acknowledgment from Device ACK ACK ACK No ACK ACK No ACK ACK Action from Device Read Array Can Write to Second Half (80H - FFH) Only Can Write to Full Array Stop - Indicates Write Protect Register is Programmed Read Out Data Don't Care. Indicates WP Register is Not Prog Stop - Indicates Write Protect Register is Programmed Program Write Protect Register (irreversible)
WP Connected to VCC 1010 1010 1010 0110 0110 0110 0110 R W W R R W W X Programmed Not Programmed Programmed Not Programmed Programmed Not Programmed ACK ACK ACK No ACK ACK No ACK ACK Read Array Device Write Protect Device Write Protect Stop - Indicates Write Protect Register is Programmed Read Out Data Don't Care. Indicates WP Register is Not Prog Stop - Indicates Write Protect Register is Programmed Cannot Program Write Protect Register
Figure 7. Setting Write Protect Register
S T A R T SDA LINE CONTROL BYTE WORD ADDRESS DATA S T O P
0110
0 A C K A C K A C K
= Don't Care
Read Operations
Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. To end the command, the microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 11 on page 13). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked
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in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. To end the command, the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 12 on page 13). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 13 on page 13). WRITE PROTECT REGISTER STATUS: To find out if the register has been programmed, the same procedure is used as to program the register except that the R/W bit is set to 1. If the device acknowledges, then the write protect register has not been programmed. Otherwise, it has been programmed and the device is permanently write protected at the first half of the array. Figure 8. Device Address
Figure 9. Byte Write
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Figure 10. Page Write
Figure 11. Current Address Read
Figure 12. Random Read
Figure 13. Sequential Read
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Ordering Information(1)
Ordering Code AT34C02-10PU-1.8(2) AT34C02N-10SU-1.8(2) AT34C02-10TU-1.8(2) AT34C02Y1-10YU-1.8(2) AT34C02U3-10UU-1.8(2) AT34C02N-10SE-2.7 AT34C02-10TE-2.7 AT34C02N-10SQ-2.7(2) AT34C02-10TQ-2.7(2) AT34C02-W1.8-11(3) Notes: Package 8P3 8S1 8A2 8Y1 8U3-1 8S1 8A2 8S1 8A2 Die Sale Operation Range Lead-free/Halogen-free/ Industrial Temperature (-40C to 85C) Automotive (-40C to 125C) Lead-free/Halogen-free/Automotive (-40C to 125C) Industrial Temperature (-40C to 85C)
1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics Tables. 2. "U" and "Q" designate Green package + RoHS compliant. 3. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing.
Package Type 8P3 8S1 8A2 8Y1 8U3-1 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8-ball, die Ball Grid Array Package (dBGA2) Options -1.8 Low Voltage (1.8V to 5.5V)
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AT34C02
Packaging Information
8P3 - PDIP
E E1
1
N
Top View
c eA
End View
D e D1 A2 A
SYMBOL
COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE
A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365
0.210 0.195 0.022 0.070 0.045 0.014 0.400
2
5 6 6
3 3
b2 b3
4 PLCS
L
D1 E E1 e eA L
b
0.325 0.280
4 3
Side View
4 0.150 2
Notes:
1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B
R
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8S1 - JEDEC SOIC
C
1
E
E1
N
L
Top View End View
e B A
SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM - - - - - - - 1.27 BSC 0.40 0 - - 1.27 8 MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE
A1
A A1 b C
D
D E1 E
Side View
e L
Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B
R
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AT34C02
8A2 - TSSOP
3 21
Pin 1 indicator this corner
E1
E
L1
N L
Top View
End View
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 - 0.80 0.19 4.40 - 1.00 - 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5
b
A
D E E1 A
e D
A2
A2 b e
Side View
L L1
Notes:
1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)
DRAWING NO. 8A2
REV. B
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8Y1 - MAP
PIN 1 INDEX AREA
A 1 2 3 4
PIN 1 INDEX AREA
E1 D D1
L 8 E A1 b 7 6 5 e
Top View
End View
Bottom View
COMMON DIMENSIONS (Unit of Measure = mm)
SYMBOL
A
A A1
MIN - 0.00 4.70 2.80 0.85 0.85 0.25
NOM - - 4.90 3.00 1.00 1.00 0.30 0.65 TYP
MAX 0.90 0.05 5.10 3.20 1.15 1.15 0.35
NOTE
Side View
D E D1 E1 b e L
0.50
0.60
0.70
2/28/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1 DRAWING NO. 8Y1 REV. C
R
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8U3-1 - dBGA2
E
D
1.
b
PIN 1 BALL PAD CORNER
A1 A2 A
Top View
PIN 1 BALL PAD CORNER
Side View
4
1 (d1)
2
3
d
8 e
7
6
5
COMMON DIMENSIONS (Unit of Measure = mm) (e1) SYMBOL MIN 0.71 0.10 0.40 0.20 NOM 0.81 0.15 0.45 0.25 1.50 BSC 2.00 BSC 0.50 BSC 0.25 REF 1.00 BSC 0.25 REF MAX 0.91 0.20 0.50 0.30 NOTE
Bottom View
8 SOLDER BALLS
A A1 A2 b
1. Dimension "b" is measured at the maximum solder ball diameter. This drawing is for general information only.
D E e e1 d d1
6/24/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Small Die Ball Grid Array Package (dBGA2) DRAWING NO. PO8U3-1 REV. A
R
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Revision History
Doc. Rev. 0958Q
Date 1/2007
Comments Revision history implemented. Added Note to Page 1: Not recommended for new design; please refer to AT34CO2C datasheet.
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Atmel Corporation
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